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74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs
April 2000 Revised November 2000
74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs
General Description
The LVTH652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level. Output Enable pins (OEAB, OEBA) are provided to control the transceiver function. (See Functional Description). The LVTH652 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. This octal transceiver/register is designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH652 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink -32 mA/+64 mA s Functionally compatible with the 74 series 652 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:
Order Number 74LVTH652WM 74LVTH652MTC Package Number M24B MTC24 Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
IEEE/IEC
(c) 2000 Fairchild Semiconductor Corporation
DS012018
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74LVTH652
Pin Descriptions
Pin Names A0-A7 B0-B7 CPAB, CPBA SAB, SBA OEAB, OEBA Description Data Register A Inputs/ 3-STATE Outputs Data Register B Inputs/ 3-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs
Connection Diagram
Truth Table
(Note 1) Inputs OEAB OEBA L L X H L L L L H H H H H H H X L L L H H L CPAB H or L CPBA H or L H or L SAB X X X X X X X X L H H SBA X X X X X X L H X X H Output Input Output Input Input Not Specified Output Output Not Specified Output Input Input Input Inputs/Outputs A0 thru A7 Input B0 thru B7 Input Operating Mode Isolation Store A and B Data Store A, Hold B Store A in Both Registers Hold A, Store B Store B in Both Registers Real-Time B Data to A Bus Store B Data to A Bus Real-Time A Data to B Bus Stored A Data to B Bus Stored A Data to B Bus and Stored B Data to A Bus
H or L X X X H or L H or L

X X X
H or L
H or L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Output
= LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVTH652
Functional Description
In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select (SAB, SBA) controls can multiplex stored and real-time. The examples below demonstrate the four fundamental bus-management functions that can be performed with the LVTH652. Data on the A or B data bus, or both can be stored in the internal D-type flip-flop by LOW-to-HIGH transitions at the appropriate Clock Inputs (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines are in a HIGH impedance state, each set of bus lines will remain at its last state.
Real-Time Transfer Bus B to Bus A
Real-Time Transfer Bus A to Bus B
OEAB L
OEBA L
CPAB X
CPBA X
SAB X
SBA L
OEAB H
OEBA H
CPAB X
CPBA X
SAB L
SBA X
Storage
Transfer Storage Data to A or B
OEAB X L L
OEBA H X H
CPAB X

CPBA
SAB X X X
SBA X X X
OEAB H
OEBA L
CPAB H or L
CPBA H or L
SAB H
SBA H

X
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74LVTH652
Absolute Maximum Ratings(Note 2)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 3) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free-Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-32
64
-40
0
85 10
C
ns/V
t/V
Note 2: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 3: IO Absolute Maximum Rating must be observed.
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74LVTH652
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) II(OD) II Bushold Input Minimum Drive Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power OFF Leakage Current Power Up/Down 3-STATE Output Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 6)
Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
TA =-40C to +85C Min 2.0 0.8 VCC - 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 75 -75 500 -500 10 1 -5 1 100 100 -5 5 10 0.19 5 0.19 0.19 0.2 Max -1.2
Units V V V V V V V V V V A A A A A A A A A A A A A mA mA mA mA mA
Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 4) (Note 5) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V VO = 0.5V to 3.0V VI = GND or VCC VO = 0.0V VO = 3.6V VCC < V O 5.5V Outputs HIGH A or B Port Outputs LOW Outputs Disabled VCC V O 5.5V Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
3.0 3.0 3.6 3.6 3.6 0 0-1.5V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3 Min
(Note 7)
TA = 25C Typ 0.8 -0.8 Max Conditions Units V V CL = 50 pF, RL = 500 (Note 8) (Note 8)
Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
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74LVTH652
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3V 0.3V Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ tW tS tH tOSHL tOSLH Maximum Clock Frequency Propagation Delay Data to Output Clock to A or B Propagation Delay Data to Output Data to A or B Propagation Delay Data to Output SBA or SAB to A or B Output Enable Time OE to A Output Disable Time OE to A Output Enable Time OE to B Output Disable Time OE to B Pulse Duration Setup Time Hold Time Output to Output Skew (Note 9) Clock HIGH or LOW Data HIGH before CP Data LOW before CP Data HIGH or LOW after CP 150 1.8 1.8 1.3 1.3 1.5 1.5 1.1 1.1 2.0 2.0 1.3 1.3 1.5 1.5 3.3 1.2 1.6 0.8 1.0 1.0 5.6 4.8 4.5 4.6 5.5 5.4 5.2 5.6 5.5 5.5 4.9 5.3 5.6 5.6 Max VCC = 2.7V Min 150 1.8 1.8 1.3 1.3 1.5 1.5 1.1 1.1 2.0 2.0 1.3 1.3 1.5 1.5 3.3 1.5 2.2 0.8 1.0 1.0 ns ns 6.2 5.6 4.9 5.2 6.4 6.1 6.5 6.6 6.1 5.9 5.7 5.8 6.7 6.3 Max MHz ns ns ns ns ns ns ns ns ns Units
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN CI/O
(Note 10)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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74LVTH652
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B
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74LVTH652 Low Voltage Octal Transceiver/Register with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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